/*
 * yauosk - Yet Another Useless Operating System Kernel
 *
 * Copyright (c) 2009-2010 Matteo Cicuttin
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 * derived from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/types.h>
#include <arch/x86/machine.h>


/* 8259s are at 0x20 (master) and 0xA0 (slave). Slave pic interrupt goes to
   interrupt 2 of the master */
#define MASTER_IO_BASE		0x20
#define SLAVE_IO_BASE		0xA0
#define SLAVE_IRQ			2

#define ICW1(flags) (0x10 | flags)

#define EDGE_TRIGGER	0
#define LEVEL_TRIGGER	0x08
#define	CASCADE_PICS	0
#define	MASTER_PIC_ONLY	0x02
#define	NO_ICW4			0
#define	ICW4_REQ		0x01

#define FULLY_NESTED	0x10
#define BUFFERED		0x08
#define SLAVE_PIC		0
#define MASTER_PIC		0x04
#define EOI_AUTO		0x02
#define MODE_X86		0x01
#define MODE_MCS		0

static ushort cached_irq_mask = 0xFFFF;

static void
irq_8259_setmask(ushort mask)
{
	cached_irq_mask = mask;

	outb(MASTER_IO_BASE+1, (char) mask);
	outb(SLAVE_IO_BASE+1, (char)(mask >> 8));
}

void
irq_8259_enable(ushort irq)
{
	cached_irq_mask &= ~(1 << irq);
	irq_8259_setmask(cached_irq_mask);
}

void
irq_8259_disable(ushort irq)
{
	cached_irq_mask |= (1 << irq);
	irq_8259_setmask(cached_irq_mask);
}

void
irq_8259_init(void)
{
	/* Start masking all interrupts */
	outb(MASTER_IO_BASE+1, 0xFF);
	outb(SLAVE_IO_BASE+1, 0xFF);
	
	/* ICW1: Master PIC operating mode */
	outb(MASTER_IO_BASE, ICW1(ICW4_REQ));
	/* ICW2: Interrupt descriptor table offset */
	outb(MASTER_IO_BASE+1, IRQ_OFFSET);
	/* ICW3: IRQ lines connected to slave PICs */
	outb(MASTER_IO_BASE+1, 1 << SLAVE_IRQ);
	/* ICW4 */
	outb(MASTER_IO_BASE+1, EOI_AUTO | MODE_X86);
	
	/* ICW1: Master PIC operating mode */
	outb(SLAVE_IO_BASE, ICW1(ICW4_REQ));
	/* ICW2: Interrupt descriptor table offset */
	outb(SLAVE_IO_BASE+1, IRQ_OFFSET+8);
	/* ICW3 */
	outb(SLAVE_IO_BASE+1, SLAVE_IRQ);
	/* ICW4: Auto-EOI on the slave can cause problems */
	outb(SLAVE_IO_BASE+1, EOI_AUTO | MODE_X86);
	
	outb(MASTER_IO_BASE, 0x68);
	outb(MASTER_IO_BASE, 0x0a);
	outb(SLAVE_IO_BASE, 0x68);
	outb(SLAVE_IO_BASE, 0x0a);
	
	irq_8259_setmask(cached_irq_mask & ~(1<<SLAVE_IRQ));
	printf("8259: configured\n");
}

